The subject matter of the present application relates to microelectronic assemblies and fabrication methods, and more particularly to the structure of and fabrication method for a low-profile microelectronic package.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel.
Each chip package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. In some designs which are referred to as “flip chip” designs, the front face of the chip confronts the face of a package substrate, and the contacts on the chip are bonded directly to contacts of the package substrate by solder balls or other connecting elements. In turn, the package substrate can be bonded to a circuit panel through terminals overlying the front face of the chip.
There are, however, applications in which a relatively larger package is desired. These include instances in which a relatively large fan-out area is needed to achieve connection to a larger array on a printed circuit board or the like. Many wafer-level packages present reliability issues in such relatively larger sizes due to an inherent increase in the effects of varying coefficients of thermal expansion among the components of the package. Such effects can also be visible in relatively smaller applications, particularly when contacts are placed in certain locations and when the package undergoes frequent heat-cycling.
Size is a significant consideration in any physical arrangement of one or more chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
In light of the foregoing, certain improvements can be made in the structure of microelectronic packages and assemblies which comprise a microelectronic package. In this regard, there remains a need for improved packages that are reliable, thin, testable and economical to manufacture.